This invention relates to digital communications systems wherein data is serially transmitted in frames of multi-bit bytes and, more particularly, to an errored frame detection arrangement for use in such a system.
A relatively new transmission standard has been developed for Synchronous Optical Network (SONET), which is derived from a base rate and format, combined with a multiplexing scheme. This results in a modular family of rates and formats available for use in optical interfaces. The base rate is known as the Synchronous Transport Signal level 1 (STS-1). Each STS-1 frame is a serial bit stream of 810 bytes, with each byte including eight bits. The STS-1 framing is dedicated to the first two bytes of each STS-1 frame. The framing pattern for bytes A1 and A2 is F628 Hex (1111011000101000), where A1 equals F6 Hex (11110110) and A2 equals 28 Hex (00101000). Higher rates (STS-N) in SONET are accomplished by byte interleave multiplexing an N number of STS-1 frames. The framing pattern for an STS-3 frame in an Optical Carrier level 3 (OC-3) system is then A1A1A1A2A2A2. Similarly, the framing pattern for an STS-12 frame in an OC-12 system is twelve A1 bytes followed by twelve A2 bytes. This framing pattern of consecutive A1 Bytes followed by consecutive A2 bytes occurs every frame, or every 125 microseconds in one example of the system.
The SONET Specification specifies three levels of frame loss: Errored Frame, Out of Frame, and Loss of Frame. The Specification states a Loss of Frame (LOF) condition shall be detected on the incoming STS-N signal when an Out of Frame (OOF) condition persists for a period of 3 milliseconds, and an Out of Frame condition on an STS-N shall be detected when four consecutive errored framing patterns have been received. An errored framing pattern is when the A1A2 framing pattern is not detected at the proper 125 microsecond interval.
The basic function of a frame recovery circuit in a communications system is to recognize and lock onto the framing pattern, provide frame lock indication, and resynchronize the receiver to the incoming data stream in a minimum amount of time.
In the past, various circuits have been used for errored frame detection in data transmission systems. However, these circuits have used emitter coupled logic and, with such logic, an undesirably large number of circuits were required. Thus, these known circuits were undesirably complex and expensive.
Accordingly, it is a primary object of this invention to provide a frame error detection circuit which utilizes such logic circuits that a minimum number of circuits are required and a less expensive and complex system results than known in the past.
Another object of this invention is to provide a frame error detection circuit which may be used in both an OC-3 and OC-12 system.